In a typical input-output (I/O) transceiver, a receiver of a processor processes a received signal to ascertain the data contained in the received signal. Such processing requires determining data and edge samples for the received signal by means of at least two phase interpolators (PIs), each phase interpolator (PI) generating a pair of clock signals. The output of the PIs is quadrature clock signals having four phases. Two of the four phases are used to sample the received data signal while the remaining two of the four phases of the quadrature clock signals are used to sample edges of the received data signal. The term “edge” herein refers to the point in time when the data signal transitions from a logical low or a logical high signal level to a logical high or a logical low signal level, respectively. Any mismatch in the delay between the four phases of the quadrature clock signals causes an effective offset in the data sampling phase resulting in increase of bit error rate (BER) and reduction in jitter tolerance for the receiver.
A typical receiver 200 is shown in FIG. 2. The receiver 200 receives input signals rxp and rxn from a transmitter e.g., 103 of FIG. 1. The received signals rxp and rxn are sampled by samplers after being equalized by optional an equalizer. The samplers receive the four phased quadrature clock signals i.e., iclk, iclkb, qclk, qclkb from a clock distribution network that distributes the quadrature clock signal from the two PIs to the samplers. The output of the samplers are data and edge samples (d0, d1 and e0, e1) which are then utilized by a clock and data recovery (CDR) circuit to generate two sets of codes (pidac1 and pidac2) to instruct the two PIs to adjust delays to the quadrature clock signals. In the CDR circuit, the delays of the quadrature clock signals are adjusted so that the iclk signal samples the data signal at the middle of the data signal eye and the qclk signal samples the edge of the data signal at the transition point of the data signal. The four phased quadrature clock signals are generated by the two PIs that receive clock signals as inputs by means of a clock distribution network. Timing mismatch between the input clock signals cki, ckib, ckq, and ckqb, which are input to the two PIs, and the four phased output quadrature clock signals iclk, iclkb, qclk, and qclkb causes an offset in the data sampling phase, thus increasing BER and decreasing jitter tolerance for the receiver.
Such timing mismatch between the input and output clock signals may be caused by systematic and random process variations in the devices used to implement the two PIs—causing a mismatch in electrical behavior (e.g., delays, rise/fall times, etc) in the two PIs even when they have identical designs. Such timing mismatch between the input (cki, ckib, ckq, and ckqb) and output clock signals (iclk, iclkb, qclk, and qclkb) may also be caused, in addition to the mismatch in the two PIs, by routing delay mismatches in the clock distribution network between the four phased quadrature clock signals iclk, iclkb, qclk, and qclkb. Such mismatch between the four phased quadrature clock signals iclk, iclkb, qclk, and qclkb is a performance limiter (performance as measured by BER, timing margin, jitter tolerance, etc.) for receivers in a processor.